Title:
半導体集積回路及びその試験を行う試験システム
Document Type and Number:
Japanese Patent JP4167497
Kind Code:
B2
Abstract:
A semiconductor integrated circuit includes a pin section, internal circuits, an interface section, an expectation value generation circuit, a comparison circuit and a waveform generation circuit. In a first test mode, the expectation value generation circuit generates expectation values of operation signals to be generated by the interface section when first test signals having the same waveform are input via respective pins of the pin section, and the comparison circuit compares operation signals that are actually produced by the interface section with the respective expectation values and produces comparison results. In a second test mode, the waveform generation circuit supplies second test signals to the interface section, and the interface section outputs test output signals having the same waveform to the external system via respective pins of the pin section.
Inventors:
Masaaki Tanimura
Application Number:
JP2003009704A
Publication Date:
October 15, 2008
Filing Date:
January 17, 2003
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
G01R31/28; G01R31/303; G01R31/317; G01R31/3193; G11C29/50; G01R31/319
Domestic Patent References:
| JP2000163991A | ||||
| JP3122578A | ||||
| JP4169874A | ||||
| JP10142298A | ||||
| JP2002350509A |
Attorney, Agent or Firm:
Mamoru Takada
Hideki Takahashi
Atsuko Oaku
Atsushi Hirayama
Tamaki Otsuka
Hideki Takahashi
Atsuko Oaku
Atsushi Hirayama
Tamaki Otsuka
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