Title:
半導体集積回路及びそのテスト方法
Document Type and Number:
Japanese Patent JP4947689
Kind Code:
B2
Abstract:
To reduce a testing time of a semiconductor integrated circuit.
The semiconductor integrated circuit 1 comprises: a RAM 2, and a control circuit 10 for controlling the retention test of the RAM 2. The control circuit 10 breaks electrical connection between the RAM 2 and other internal circuits 3 during the retention test. Then, after the retention test is completed, the control circuit 10 secures electrical connection between the RAM 2 and an output terminal OUT, and outputs data held by the RAM 2 to the output terminal OUT.
COPYRIGHT: (C)2008,JPO&INPIT
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Inventors:
Koriyama Kazuhiro
Application Number:
JP2006129829A
Publication Date:
June 06, 2012
Filing Date:
May 09, 2006
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H01L21/822; G01R31/28; G11C29/56; H01L27/04
Domestic Patent References:
| JP1062501A | ||||
| JP1123672A | ||||
| JP2002304898A | ||||
| JP2000200874A |
Attorney, Agent or Firm:
Minoru Kudo