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Title:
SEMICONDUCTOR INTEGRATED MEMORY CIRCUIT AND LATCH CIRCUIT TRIMMING METHOD
Document Type and Number:
Japanese Patent JP2010055653
Kind Code:
A
Abstract:

To provide a semiconductor integrated memory circuit capable of trimming all varied threshold value voltages of a plurality of latch circuits together, and a trimming method using the same.

The semiconductor integrated memory circuit includes a latch circuit formed by cross-coupling first and second inverters with first and second nodes, and a voltage application circuit for applying hot carrier generation voltages to the first and second nodes. The circuit further includes an inversion circuit for generating an inverted signal obtained by inverting an amplification signal output from the latch circuit.


Inventors:
Kawasumi, Atsushi
Application Number:
JP2008000216198
Publication Date:
March 11, 2010
Filing Date:
August 26, 2008
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
G11C11/419; H03K3/356
Domestic Patent References:
JPH0676582A1994-03-18
JP2000311491A2000-11-07
JP2005276315A2005-10-06
JP2005353106A2005-12-22
JP2004127499A2004-04-22
JP2003045190A2003-02-14
Attorney, Agent or Firm:
伊丹 勝
田村 和彦