Title:
半導体集積メモリ装置
Document Type and Number:
Japanese Patent JP3997042
Kind Code:
B2
Abstract:
With this arrangement the power supply leads (10) to the individual memory cell fields (1-8) are high resistance (long) whilst those between the individual fields are low resistance (short) leads (11-14). When a specific field is activated it draws its supply from the capacitance of the inactive fields through the low resistance leads. The depletion in stored power is replenished continually through the high resistance leads
Inventors:
Atanacia Chrysostomides
Robert Foillet
Robert Kaiser
Helmut Schneider
Robert Foillet
Robert Kaiser
Helmut Schneider
Application Number:
JP2000038348A
Publication Date:
October 24, 2007
Filing Date:
February 16, 2000
Export Citation:
Assignee:
Infineon Technolgies SC300 GmbH & Co.KG
International Classes:
H01L27/10; G11C5/02; G11C5/14; G11C7/00; H01L21/8242; H01L23/528; H01L27/02; H01L27/105; H01L27/108
Domestic Patent References:
| JP11017135A | ||||
| JP10303389A | ||||
| JP11340438A |
Attorney, Agent or Firm:
Toshio Yano
Toshiomi Yamazaki
Takuya Kuno
Einzel Felix-Reinhard
Reinhard Einsel
Toshiomi Yamazaki
Takuya Kuno
Einzel Felix-Reinhard
Reinhard Einsel