PURPOSE: To prevent malfunction due to an unsharpened signal waveform of a data input signal due to a parasitic resistance and a parasitic capacitance of a wire even when a duty ratio of a clock signal is changed a little by inputting an output of a duty correction circuit as a control signal of a post-stage successive logic circuit.

CONSTITUTION: An input signal SD1 is inputted as data of a pre-stage D flip-flop circuit 1 whose output changes at a leading of a clock signal SC and a clock signal SC is inputted to a clock terminal C. With a control signal SG at an H level, input data SD2 is outputted as a signal SQ2 from an output terminal Q and with the control signal SG set to an L level, the input signal SD2 through a signal wire 8 is inputted to a latch circuit 2 latching the content of latch and an output signal SG of a duty correction circuit 3 is inputted to a control terminal G. The duty correction circuit 3 outputs a control signal SG with a waveform in which the duty ratio is expanded and corrected.