Title:
障壁層の形成を含む半導体製造方法
Document Type and Number:
Japanese Patent JP3663128
Kind Code:
B2
Abstract:
A semiconductor processing method includes forming a conductively doped plug (28, 30) of semiconductive material within a first insulative layer (26). A barrier layer (25) to out diffusion of dopant material from the semiconductive material is formed over the doped plug (28, 30). Examples include undoped oxide, such as silicon dioxide, and Si3N4. A second insulative layer (32) is formed over the barrier layer (25). Conductive material (60) is formed through the second insulative layer (32) and into electrical connection with the doped plug (30). In another implementation, spaced first and second conductively doped regions (28, 30) of semiconductive material are formed. A barrier layer (25) to out diffusion of dopant material from the semiconductive material is formed over at least one of the first and second regions (28, 30), and preferably over both. Then, a capacitor having a capacitor dielectric layer (42) comprising Ta2O5 is formed over the other of the first and second regions. Conductive material (60) is formed over and in electrical connection with the one of the first and second regions (30).
Inventors:
Parek, Kunal, Earl.
Sakuru, Landhar, P., S.
Sakuru, Landhar, P., S.
Application Number:
JP2000525914A
Publication Date:
June 22, 2005
Filing Date:
December 18, 1998
Export Citation:
Assignee:
APPLIED MATERIALS,INCORPORATED
International Classes:
H01L21/02; H01L21/768; H01L21/8242; H01L21/283; H01L23/522; H01L27/108; (IPC1-7): H01L21/283; H01L21/8242; H01L27/108
Attorney, Agent or Firm:
Masanori Ishihara