SEMICONDUCTOR MEMORY AND CACHE MEMORY DEVICE

Japanese Patent JP3489967

B2

PROBLEM TO BE SOLVED: To improve the throughput and to reduce the power consumption of a system using a micro processor provided with a cache memory.
SOLUTION: A write back buffer 20 is provided in a cache memory cell array 2. The memory cell of the same line is selected in the cache memory cell array 2 by an arbitrary word line and all data to be saved are simultaneously and collectively written into the write back buffer 20 through a pair of bit lines. Since data to be saved can be written into the write back buffer 20 without the aid of a data bus 7, the number of times for accessing the cache memory 2 can considerably be reduced, the throughput can be improved, and the power consumption of the micro processor can be reduced. Since the write back buffer 20 is constituted of the memory cells, the chip area can be reduced.

Hiroaki Okuyama

JP14955797A

January 26, 2004

June 06, 1997

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Matsushita Electric Industrial Co., Ltd

G11C11/41; G06F12/08; G06F15/78; G11C11/401; G11C11/419; (IPC1-7): G06F12/08; G11C11/401; G11C11/41

JP676578A
JP5274863A
JP3113893A

Hiroshi Maeda (2 outside)

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