Title:
SEMICONDUCTOR MEMORY CELL AND ITS MANUFACTURE
Document Type and Number:
Japanese Patent JP2526770
Kind Code:
B2
Abstract:
PURPOSE: To avoid crackings in a layer insulating film under a capacitor and decrease of the film thickness by a method wherein a cylindrical node electrode is formed on a MOS transistor with the layer insulating film therebetween and the node electrode side uppermost layer of the layer insulating film is composed of an etching-proof film.
CONSTITUTION: A node electrode 16 is composed of a first N-type polycrystalline silicon film 13a connected to an N-type node diffused layer 5, a cylindrical second N-type polycrystalline silicon film 13b and a cylindrical third N-type polycrystalline silicon film 13c. A cell-plate 18 and a bit line 8 are separated from each other with a layer insulating film 10 and a boron silicate glass film 11 which is an etching-proof film. With this constitution, very little stress is produced in the interlayer film and crackings are not developed. Further, hydrogen for a hydrogen treatment for the reduction of an interfacial level can be supplied sufficiently. Moreover, a constriction in the contact which is produced in a pre-treatment for forming a conductor film in the contact hole of the node electrode can be avoided.
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Inventors:
Tsuru Masahiro
Application Number:
JP31961592A
Publication Date:
August 21, 1996
Filing Date:
November 30, 1992
Export Citation:
Assignee:
NEC
International Classes:
H01L27/04; H01L21/822; H01L21/8242; H01L27/10; H01L27/108; (IPC1-7): H01L27/108; H01L21/822; H01L21/8242; H01L27/04
Domestic Patent References:
| JP425170A | ||||
| JP426156A | ||||
| JP499373A |
Attorney, Agent or Firm:
Sugano Naka