Title:
SEMICONDUCTOR MEMORY CELL
Document Type and Number:
Japanese Patent JP3142763
Kind Code:
B
Abstract:
PROBLEM TO BE SOLVED: To improve the degree of integration of a chip by reducing the number of used elements by constituting an SRAM cell of three PMOS transistors and one capacitor.
SOLUTION: When a work line W/L becomes a low state, PMOS transistors(Trs) T1 and T2 are turned on and the high potential at a bit line BL is transmitted to a node C. In addition, the low potential at another bit line BLB is transmitted to another node D. Therefore, a capacitor C1 is charged with the high potential at the node C and high-state data are written in an SRAM cell. When the data are written in the SRAM cell, the cell constantly maintains the high-state data in a sable state, because the low state of the node D is impressed upon the gate of a PMOS Tr T3 and the Tr T3 is maintained in a turned-on state. When the word line W/L becomes a low state, on the other hand, the Trs T1 and T2 are turned on and a low potential is transmitted to the node C. In addition, a high potential is transmitted to the node D and the Tr T3 is turned off.
Inventors:
Kin, Tatsushu
Application Number:
JP1995000336557
Publication Date:
December 22, 2000
Filing Date:
December 25, 1995
Export Citation:
Assignee:
LG SEMICON CO LTD
International Classes:
G11C11/412; G11C11/34; G11C11/402; (IPC1-7): G11C11/412