PURPOSE: To eliminate the same number of bus lines as a pit width by discriminating whether data in the high level or in the low level should be written in a memory cell or write should be inhibited.

CONSTITUTION: The threshold level of an inverter I1 is set to 3/4 of a supply voltage VCC, and that of an inverter I2 is set to 1/4 VCC. When a line DATA is in the high level (VCC)/the low level (0V), nodal points N1 and N2 go to the low level/the high level, and an output nodal point N3 of a NOR gate NR1 goes to the high level, and data on the line DATA is transmitted to complementary signal lines D and D*. As the result, data is written in a selected cell in a memory cell array 100. Meanwhile, when the line DATA is in the intermediate level (1/2VCC), the nodal point N1 goes to the high level, and the nodal point N2 goes to the low level, and therefore, the nodal point N3 of the NOR gate NR1 goes to the low level to set the write inhibiting state.