Title:
SEMICONDUCTOR MEMORY, CONTROL METHOD FOR OUTPUT SIGNAL IN SEMICONDUCTOR DEVICE, AND OUTPUT SIGNAL CONTROL CIRCUIT
Document Type and Number:
Japanese Patent JP3762558
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To surely prevent erroneously sensing data due to the occurrence of an output noise by variation of power source voltage, when a sense amplifier performs data-sensing.
SOLUTION: This device is provided with a signal delay means 100 that makes an output control signal/OE of an external input inputted from the outside not to be transmitted to an output buffer 6 for a prescribed period after change of an address, in the prescribed period after an address AD is changed, malfunctions caused by occurrence of an output noise, while the sense amplifier 1 performs data-sensing is prevented by preventing inversion of a logic level of a signal 'OUT' outputted from the output buffer 6, when the sense amplifier 1 performs data-sensing.
Inventors:
Kurosaki Kazuhide
Application Number:
JP37190298A
Publication Date:
April 05, 2006
Filing Date:
December 28, 1998
Export Citation:
Assignee:
富士通株式会社
International Classes:
G11C11/41; G11C16/06; G11C7/10; G11C7/22; H03F1/26; H03F3/18; (IPC1-7): G11C16/06; G11C11/41; H03F1/26; H03F3/18
Domestic Patent References:
| JP3037699U | ||||
| JP4089699A | ||||
| JP4259997A | ||||
| JP8063970A | ||||
| JP64017298A |
Attorney, Agent or Firm:
Takayoshi Kokubun