PURPOSE: To reduce a redundancy address decoder by selecting a redundancy memory in response to a bit of an address signal line, and replacing a defective memory with the redundancy memory.

CONSTITUTION: A peripheral circuit reads information from a memory cell 46, and again writes the information. The circuit responds to a defective row group address of the cell 46 and selects a redundancy row group of the cell 46 of only a memory array 12 having a defective row group of the cell 46. A redundancy circuit selects one or more redundancy row line in the redundancy row group so as to replace a defective bit. A predetermined bonding pad is connected to a VSS via a bonding wire to be selected by redundancy memory address decoders 82, 84, 88, 92. Fuse decoders 84, 86, 90, 92 can replace defective data of other memory cells with selected redundancy memory data. Then, since all the bits and all row addresses are used, the decoders 82, 84, 88, 92 can be reduced.