PURPOSE: To correct the error of information by outputting the information of a bit line pair in inverting it, respectively, according to that the error is detected.
CONSTITUTION: By checking the data of respective bit line pairs, an error detecting circuit 30 generates a signal SY0 and conducts transistors 26 and 27 when the error is detected in, for example, a 0-th bit line pair BL0 and BL0. The output of an inverting amplifier 15 is outputted through the transistor 27 to the bit line pair BL0, the output of an inverting amplifier 14 to invert the information of the inverse of bit line BL0 is outputted through the transistor 26 to the inverse of bit line BL0, and the information of the bit line pair BL0 and BL0 is inverted. The information to be inverted in such a way is outputted to the corresponding bit line pair, and the information of the bit line pair is compulsorily rewritten. Thus, an error correcting circuit can be built in a semiconductor memory without increasing the number of I/O bus line pairs, and the error can be detected and corrected at a high speed.
FURUYA KIYOHIRO
ARIMOTO KAZUTAMI
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