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Title:
SEMICONDUCTOR MEMORY DEVICE INCREASING DENSITY OF ARRAY OF PAIR TRANSISTORS
Document Type and Number:
Japanese Patent JP2005347578
Kind Code:
A
Abstract:

To prevent a layout area from being expanded while preventing characteristics of pair transistors from being deteriorated in a semiconductor memory device continuously arraying a plurality of pair transistors each including a predetermined function.

A semiconductor memory device repeatedly arraying a plurality of pair transistors each including a predetermined function includes a plurality of pair transistors comprised of transistors adjacent in a row direction, a plurality of pair transistors comprised of transistors of which a mutual arrangement relationship is oblique, and a group of pair transistors arraying the plurality of pair transistors combining them.


Inventors:
SEKINE JUNICHI
Application Number:
JP2004166349A
Publication Date:
December 15, 2005
Filing Date:
June 03, 2004
Export Citation:
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Assignee:
ELPIDA MEMORY INC
International Classes:
H01L21/8242; G11C5/06; G11C11/401; G11C11/412; H01L27/108; (IPC1-7): H01L21/8242; G11C11/401; H01L27/108
Attorney, Agent or Firm:
Kawaguchi Maki