SEMICONDUCTOR MEMORY DEVICE AND ITS TESTING METHOD

Title:

SEMICONDUCTOR MEMORY DEVICE AND ITS TESTING METHOD

Document Type and Number:

Japanese Patent JP2007213659

Kind Code:

A

Abstract:

To shorten fatigue testing time while suppressing the increase in a chip area.

In the fatigue test, data are rewritten to "0"→"1"→"0" with respect to a ferroelectric capacitor Cxx0 and rewritten to "1"→"0"→"1" with respect to a ferroelectric capacitor Cxx1. Transfer gates CT00, CT01, ..., are used for supplying a reference potential Vref by utilizing a path to be used in a Vref applying test and further the reference potential Vref is supplied from the outside of ferroelectric memory chip via a pad. Consequently, there is no need of considering driving ability of a transistor of which the supply of potential for the fatigue test is formed inside the ferroelectric memory chip such as a write buffer, the fatigue testing time can be shortened while suppressing the increase in the area of ferroelectric memory chip.

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Inventors:

TAKAHASHI KAZUHIKO

Application Number:

JP2006030496A

Publication Date:

August 23, 2007

Filing Date:

February 08, 2006

Export Citation:

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Assignee:

OKI ELECTRIC IND CO LTD

International Classes:

G11C29/06; G01R31/28; G11C11/22

Attorney, Agent or Firm:

Kakimoto Yasunari

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