PURPOSE: To improve the controllability of threshold voltage by selectively forming the other conductivity type buried layer in high impurity concentration to one conductivity type silicon substrate in low impurity concentration while shaping a memory region to a substrate body with an epitaxial layer.

CONSTITUTION: A second conductivity type second semiconductor region buried layer 10b is formed onto a first conductivity type first semiconductor source region 10a, and a first conductivity type third semiconductor region is shaped onto the layer 10b as an epitaxial layer 10c, thus forming a semiconductor substrate body 11. A latticed groove 15 is shaped to the substrate body 11 to form a plurality of insular regions 17, and a first insulating film 23 is shaped selectively only on the bottom of the groove 15. Second insulating layers 29 and first conductive films 27 are formed to lower-section side walls, fourth insulating films 31 onto the first conductive films 27 and the top faces of insular regions 17, third insulating films 37 to the upper-section side walls of the groove 15, second conductive films 33 onto the films 37 and second conductivity type fourth semiconductor regions 35 into the top face regions of the insular regions 17, and a third conductive film 43 brought into contact with contact holes 41 is shaped through the contact holes 41. Accordingly, the controllability of threshold voltage can be improved.