To provide a semiconductor memory device in which capacitance of a capacitor is lower and integration degree is higher.

A plurality of memory blocks is connected to one bit line BL_m. A memory block in the n-th line includes a sub bit line SBL_n_m, and a plurality of memory cells, which connect a transistor to a capacitor in series and connect one electrode of the capacitor to the sub bit line SBL_n_m. The memory block in the n-th line includes a write transistor WTr_n_m and read transistor RTr_n_m, and the read transistor RTr_n_m is connected to an amplifier circuit AMP_n_m such as a complementary inverter. The potential change of the sub bit line SBL_n_m is amplified by the amplifier circuit AMP_n_m. Because of a sufficiently low capacitance of the sub bit line SBL_n_m, potential change due to electric charges of the capacitor in each memory cell can be amplified by the amplifier circuit AMP_n_m without an error, and the amplified data can be output to the bit line BL_m.