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Title:
SEMICONDUCTOR MEMORY, SEMICONDUCTOR DEVICE, AND TEST METHOD FOR SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JP2004014037
Kind Code:
A
Abstract:

To make a mutual interference test between memory blocks easy.

In a delay operation mode, a selection signal in accordance with a register value of a MRS register 130 is outputted, selectors 121, 123 select an external control signal, and output it to a bank 0(111) to be tested. On the other hand, selectors 122, 124 select a delay control signal being an output of a delay circuit 140, and output it to a bank (112) not to be tested. In the case of an automatic test mode, a selection signal in accordance with the MRS register 130 is outputted, the selectors 121, 123 select an external control signal, and output it to the bank 0(111). In an incorporated test circuit 150, an internal control signal in accordance with an operation pattern previously set is generated, the selector 124 selects an internal control signal outputted from the incorporated test circuit 150, and outputs it to a bank 1(112).


Inventors:
TAMURA ATSUSHI
Application Number:
JP2002167066A
Publication Date:
January 15, 2004
Filing Date:
June 07, 2002
Export Citation:
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Assignee:
SONY CORP
International Classes:
G11C29/00; G11C29/12; H01L21/822; H01L27/04; G01R31/28; (IPC1-7): G11C29/00; G01R31/28; H01L21/822; H01L27/04
Attorney, Agent or Firm:
Takeshi Hattori