Title:
SEMICONDUCTOR MEMORY DEVICE AND TESTING METHOD THEREFOR
Document Type and Number:
Japanese Patent JP3910078
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To detect a standby-current-defective but normally-operable memory cell and repair standby current abnormality.
SOLUTION: Memory power supply lines (MVDLa, MVDLb) are disconnected from a power supply node by using switch gates (15a, 15b) in a test operation, Voltages of the memory power supply lines are detected using detection holding circuits (16a, 16b). When the detected voltage is lower than a predetermined value, the corresponding memory power supply line is driven to a ground voltage level. Thereby, a standby-current-defective but normally-operable memory cell is forced to an operation-defective state.
Inventors:
Shigeru Obayashi
Yoji Kashihara
Ukita
Yoji Kashihara
Ukita
Application Number:
JP2002043531A
Publication Date:
April 25, 2007
Filing Date:
February 20, 2002
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
G01R31/28; G01R31/3185; G11C29/12; G11C11/413; G11C29/00; G11C29/04; G11C29/50; (IPC1-7): G11C29/00; G01R31/28; G01R31/3185; G11C11/413
Domestic Patent References:
| JP2001101893A | ||||
| JP10199290A | ||||
| JP9017194A | ||||
| JP61189473A |
Attorney, Agent or Firm:
Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai