To provide a semiconductor memory device which assures high-speed data read and write operations.

The semiconductor memory device of the present invention comprises the data bus 90 which is the data line provided in the hierarchical structure, and an I/O line 80. With the column selecting operation, the stored data of memory cell is transmitted to the data bus 90 via the data bus driver 70 from the I/O line 80. Prior to the column selecting operation, the data bus 90 is equalized with an equalizing circuit 60. The equalizing circuit 60 includes an equalizer capacitor Ceq for previously holding the potential corresponding to the inverting condition of the data bus 90 and a transistor gate 63 for connecting the equalizer capacitor Ceq and data bus 90.