To provide a semiconductor memory device for realizing a reduction of a power consumption and an acceleration of an operation.

The semiconductor memory device comprises ferroelectric memory cells FMC9 connected between capacitor plate, lines CP1a to CP4a and CP1b and CP2b and bit lines BL1 to BL6, and formed on a substrate to read/ write data in response to potentials of word lines WL1 to WL4 and capacitor plate lines CP1a to CP4c and CP1b and CP2b. The memory device also comprises word lines WL1 to WL4 including at least two parts at different positions in a bit line direction on the substrate.