To provide a semiconductor memory device provided with eight memory blocks.
This device is provided with eight memory blocks 20a-20h arranged at peripheral regions 11-18 excluding a central region 19 out of nine regions divided into three rows and three columns on a semiconductor substrate, a first row memory block group, a first data bus 22a constituted by extending linearly a plurality of data lines between a second row memory block group and the first row memory block group, and a second data bus 22b constituted by extending linearly a plurality of data lines between the second row memory block group and a third row memory block group, the eight memory blocks comprises four memory blocks 20a-20c, 20e arranged being adjacent the first data bus and connected to the first data bus, and four memory blocks 20b, 20f-20h arranged being adjacent the second data bus and connected to the second data bus.
SHIMODA MASAKI
TSUKIKAWA YASUHIKO
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