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Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JP2003187581
Kind Code:
A
Abstract:

To provide a semiconductor memory device solving deteriorating of a holding characteristic of information by a leak current when a cell in a DRAM is made finer and hardness of making he device have large capacity for increasing a standby current of an SRAM cell using an S type negative resistive element.

A level holder consisting of the S type negative resistive element D and a resistor R is added to a memory cell MC consisting of a capacitor C and a MOS transistor MN. A standby current of the level holder is made a leak current of MOS of 100 fA in the worst case, and a standby current of a whole chip in high integration of 1G bits or more is suppressed. As when a current of the level holder is reduced, information of a cell is destroyed at read-out, a sense amplifier is provided in all bit lines for rewriting. Therefore, refresh is not required, high integration is obtained, and high speed operation can be performed.


Inventors:
Sekiguchi, Tomonori
Matsuoka, Hideyuki
Application Number:
JP2001000387661
Publication Date:
July 04, 2003
Filing Date:
December 20, 2001
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G11C14/00; H01L21/8242; H01L27/10; H01L27/108; G11C14/00; H01L21/70; H01L27/10; H01L27/108; (IPC1-7): G11C14/00; H01L21/8242; H01L27/10; H01L27/108