To provide a semiconductor memory device in which forming operation, set/reset operation, and read-operation can be performed normally even when a defective memory cell is present.

The semiconductor memory device comprises: a memory cell array 100 in which memory cells MC are arranged at crossing parts of bit lines BL and word lines WL; an isolation latch 63 for bringing bit lines BL into a floating state in which voltage is not applied, based on an address signal; and a second isolation latch 83 setting the word lines WL to a floating state in which voltage is not applied, based on the address signal. During execution of forming operation in which the resistance state of a variable resistance element VR is set to a transition-enabled state with respect to a selection memory cell MC_11, the isolation latches 63, 83 brings the bit lines BL_0 and the word lines WL_2 to which a defective memory cell CPF is connected into a floating state.