To start a read latch circuit as quickly as possible while securing a margin for erroneous operation no matter what the size of a memory is.

A semiconductor memory device includes a memory cell array 1 including a memory cell transistor MC, an output latch circuit 3, a dummy memory cell (DC) 6, a CMOS inverter 4, and a read control circuit 5. The output latch circuit 3 is activated by an output enable signal OEN when information is read out from the memory cell transistor MC. In the dummy memory cell (DC) 6, a plurality of unit transistors are connected to a dummy bit line DBL so that current capability between the cells is equal to that of the memory cell transistor MC.