Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JP2570203
Kind Code:
B
Abstract:
PURPOSE: To enable tests of a normal memory cell array and redundant memory cell array to be carried out in the same operation mode, to shorten the test time, to reduce the chip area, and to improve the degree of freedom of test pattern.
CONSTITUTION: A redundant word line selecting circuit 4 is constituted so that, when a bit X (m+1) of a row address signal is a '1' level, the prescribed word line out of plural redundant word lines RWL is made to be at a selecting level conforming to the prescribed bit of a row address signal ADr (X0-Xm), while a redundant circuit activating signal RCA is made to be at a activating level. When the redundant circuit activating signal RCA is at a non-activation level, a word line WL of a normal memory cell array 1 is made to be at a selecting level by the row address signal ADr (X0-Xm). Therefore, before a defective address is set to a fuse circuit 41, a normal memory cell array 1 and a redundant memory cell array 2r can be simultaneously tested in the same operation mode.
Inventors:
Tsukada, Shuichi
Application Number:
JP1994000287728
Publication Date:
October 24, 1996
Filing Date:
November 22, 1994
Export Citation:
Assignee:
NEC CORP
International Classes:
G11C11/401; G11C29/00; G11C29/04; G11C29/24; G11C29/46; (IPC1-7): G11C29/00; G11C11/401