Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JP3094916
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To prevent a through current to a ROM cell in writing by specifically structuring a ROM cell formed in the same chip as a RAM cell.
SOLUTION: The semiconductor memory device is so structured that a RAM cell 101 and a ROM cell 103 connected between a plurality of word lines W1-Wn and bit lines B, /B are formed in one and the same chip. Then, the ROM cell 103 consisting of N type transistors 1, 2, 3 is formed by deleting a part of the pattern of the RAM cell 101. Writing is executed in such way that, after the bit lines B, /B are precharged, a word line W is selected by an address decoder 111, with data written in the bit lines B, /B by a write buffer 113 and outputted. When the bit lines B, /B are each 'H' and 'L', the transistor 3 is off, with the bit line B remaining in 'H'. When the bit lines B, /B are each 'L' and 'H', the transistor 3 is on, with the bit line B held in 'L'.
Inventors:
Noboru Kawamata
Application Number:
JP19472696A
Publication Date:
October 03, 2000
Filing Date:
July 24, 1996
Export Citation:
Assignee:
NEC
International Classes:
G11C16/06; G11C11/401; G11C11/41; G11C16/04; G11C17/00; H01L27/10; (IPC1-7): G11C16/04; G11C11/41
Domestic Patent References:
| JP5427331A | ||||
| JP60182596A | ||||
| JP684381A | ||||
| JP6193896U |
Attorney, Agent or Firm:
Nobuyuki Kaneda (2 others)