Title:
半導体記憶装置
Document Type and Number:
Japanese Patent JP4909619
Kind Code:
B2
Abstract:
A semiconductor memory device includes first and second global bit lines; first, second, third and fourth local bit lines; first, second, third and fourth hierarchical switches for respectively connecting the first global bit line and the first local bit line to each other, the second global bit line and the second local bit line to each other, the first global bit line and the third local bit line to each other, and the second global bit line and the fourth local bit line to each other; and first and second precharge circuits for respectively precharging the first and second global bit lines. When a memory cell connected to the first local bit line is read, the third hierarchical switch is turned off, and the first precharge circuit terminates its precharge operation after the third hierarchical switch is turned off and before a selected word line connected to the memory cell to be read is activated.
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Inventors:
Shin Iida
Application Number:
JP2006111197A
Publication Date:
April 04, 2012
Filing Date:
April 13, 2006
Export Citation:
Assignee:
Panasonic Corporation
International Classes:
G11C11/4091; G11C11/4097
Domestic Patent References:
| JP200036194A | ||||
| JP11260060A |
Attorney, Agent or Firm:
Hiroshi Maeda
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Atsushi Fujita
Kazunari Ninomiya
Tomoo Harada
Iseki Katsumori
Seki Kei
Yasuya Sugiura
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Atsushi Fujita
Kazunari Ninomiya
Tomoo Harada
Iseki Katsumori
Seki Kei
Yasuya Sugiura