PURPOSE: To enhance the data transmission speed of the title memory device without a need for changing over and connecting an I/O line pair to a data line by a method wherein I/O line pairs installed outside individual memory regions situated at both ends in the arrangement direction of a plurality of memories are connected to the same data line.
CONSTITUTION: When, e.g. mats 1, 3 are activated, either an amplifier 21 or an amplifier 22 and wither an amplifier 23 or an amplifier 24 are activated. When mats 1, 4 are substantially of the same structure, a set composed of the amplifiers 21, 23 and a set composed of the amplifiers 22, 24 are activated. When the amplifiers 21, 23 are activated, a piece of data in a memory cell in the mat 1 is read out via a bit-line pair, a sense amplifier, an I/O line pair, the amplifier 21 and a data line 31, and a piece of data in the mat 3 is read out through a bit-line pair, a shaded sense amplifier an I/O line pair 13, the amplifier 23 and a line 32. Pieces of data are written by reversing said routes. When the mats 2, 4 are activated, a readout operation and a write operation are performed in the same manner.
WADA ATSUSHI
ISHIZUKA YOSHIYUKI
