PURPOSE: To obtain a sufficient signal quantity while suppressing an increase of a layout area and simplifying production stages as well as to promote speeding up and to enhance reliability by adopting special constitution to a memory array with a static type RAM of a high-resistance load type.

CONSTITUTION: A latch is formed in a memory cell MC by crossing and coupling driving MOSFETs N1 to N4 of an N channel type and a pair of load resistance type inverters V1 consisting of high resistors R1, R2 disposed on the drain side thereof. The static type RAM is constituted by disposing a pair of selected MOSFETs P1 to P4 between complementary bit lines B0 to Bn corresponding to the non-inversion and inversion input and output nodes of this latch. The selection level of a word line W is set at a grounding potential and the H level of the writing signal transmitted via the complementary bit line B is transmitted to the input and output nodes of the latch without lowering the level by the threshold voltage of the selected MOSFET, by which the H level of the node is rapidly raised up to the prescribed level. As a result, the desired cell is obtd.