Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JPH1173776
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To realize a semiconductor memory device capable of generating an optimal equalized pulse width in accordance with the constitution of a memory, controlling the equalized pulse width in correspondence to the fluctuation of a power source voltage and the variance of a process and improving an operational speed. SOLUTION: An equalized pulse SEQP is set at a high level with a pulse width optimizing circuit 60 in accordance with a pulse SEON from a timing generating circuit 70, an equalizing operation is executed with an equalizing circuit 40 in accordance with this, and potentials of a bit line BL and a bit complementary line BLB are risen. Potentials of the bit line BL and the complementary bit line BLB are compared with a prescribed reference voltage during the equalizing operation. Since the equalized pulse SEQP is switched from the high level to a low level with the pulse width optimizing circuit 60 to finish the equalizing operation when these potentials reach the reference voltage, the equalized pulse SEQP having the optimal width is generated.
Inventors:
MORIYAMA KATSUTOSHI
Application Number:
JP23255397A
Publication Date:
March 16, 1999
Filing Date:
August 28, 1997
Export Citation:
Assignee:
SONY CORP
International Classes:
G11C11/41; G11C11/407; G11C11/409; (IPC1-7): G11C11/41; G11C11/409
Attorney, Agent or Firm:
Takahisa Sato
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