Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JPH1196078
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To attain secrecy protection and forgery prevention for each data area among plural data areas at a memory part by respectively providing passwords in one-to-one correspondence to the respective data areas. SOLUTION: The password of a data area (a) corresponds to a password A of a password area A, and the password of a data area (b) corresponds to a password B of the password area B. It is discriminated by an address discriminating part 6 the inputted address shows the data area (a), and an address storing the password in the data area (a) is selected through a column decoder part 2 and a row decoder part 3. The password A in the password area A is read out by a read/write part 4 and sent to a password collating part 5. At the password collating part 5, the password inputted from the outside is collated with the password A in the password area A. The collated result is sent to address discriminating part 6 and when the passwords are coincident, a permit flag at the address discriminating part 6 is turned on.
Inventors:
YAJIMA SHINJI
Application Number:
JP25740697A
Publication Date:
April 09, 1999
Filing Date:
September 24, 1997
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G06F12/14; G06F21/62; G06F21/79; G06K17/00; (IPC1-7): G06F12/14; G06K17/00
Attorney, Agent or Firm:
Yoshihiro Morimoto