PURPOSE: To improve the memory holding function even with small area by composing electrodes for controlling vertical FETs disposed between condensers for storing charge connected with signal wires for writing and reading out at the crossing points of a bit wire and a word wire.
CONSTITUTION: Memory cells are formed at the crossing points of a bit wire 23 and a word wire conductor 24 formed on a semiconductor substrate 21. A hole is formed at the crossing point of the bit wire 23 at the conductor 24, and a columnar semiconductor post 25 is passed through the hole. The post 25 is formed at the upper and lower parts of N type regions 26, 27 of low specific resistance, one end is connected to the bit wire 23 and the other end is connected to a semiconductor 28 forming a condenser. The semiconductor 28 is n type low specific resistance, isolated by the substrate 21 and an insulating film 22, and the electrostatic capacity from the substrate is utilized for storing the memory charge. The P type region of the post 25 is isolated by the word wire 24 and a thin insulating film 29, and the outer periphery forms a channel in an FET.
MIYAO MASANOBU
TOKUYAMA TAKASHI
| JPS57103350A | 1982-06-26 | |||
| JPS5636164U | 1981-04-07 | |||
| JPS53121480A | 1978-10-23 |