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Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JPS6089965
Kind Code:
A
Abstract:

PURPOSE: To obtain a device of high integrating density by forming a dynamic FF type memory device to which a plurality of signals are supplied with a first and a second MISFETs which are switched by the selection signal and a third and a fourth MISFETs which are switched by the other selection signal.

CONSTITUTION: The MISFET elements Q1 and Q2 for driving and MISFET elements for transmission Q3 and Q4 are formed on a semiconductor substrate, and the diffusion layers 2a, 2b, 2c consisting of polycrystalline Si are also provided for connecting these elements. Here, the layer 2a is used for power supply line, 2b for connecting the elements Q1 and Q2, Q3 and Q4, and moreover the load resistors R1 and R2. The layer 2c is used as the word line, and the resistors R1 and R2 are respectively formed by the polycrystalline Si layers 3a and 3b. In addition to such elements, the Al electrode wirings 5a∼5c for true digit line, earth line are bar digit line are provided and moreover the contact portions 6a, 6b and 7a, 7b are respectively formed.


Inventors:
YASUI NORIMASA
SHIMIZU SHINJI
NISHIMURA KOUTAROU
Application Number:
JP13715084A
Publication Date:
May 20, 1985
Filing Date:
July 04, 1984
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G11C11/412; H01L21/8238; H01L21/8244; H01L27/092; H01L27/10; H01L27/11; (IPC1-7): G11C11/40; H01L27/08; H01L27/10
Domestic Patent References:
JPS5352027A1978-05-12
Attorney, Agent or Firm:
Katsuo Ogawa