PURPOSE: To obtain memory architecture where power loss are reduced by limiting the number of memory cells which are selected after a row line has been energized.

CONSTITUTION: The memory array of an integrated circuit memory 1 is divided into plural blocks or sub-arrays 12. Row line repeaters 15 having a latch are arranged between the respective sub-arrays, so that the row line from a row decoder 14 or from the preceding sub-array is linked to the succeeding sub-array. The row line repeaters are controlled, in accordance with a part of a column address. After all the selected rows have been energized, the row line repeaters which is not related to the selected sub-array deenergize the row line in their output ends. The row line repeaters which are related to the selected sub-array keeps the selected row line to be in an energizing state. Another kind of control for the row line repeaters from a power-on reset circuit 24 is executed.