PURPOSE: To prohibit the enable operation, a special mode, during a power up.

CONSTITUTION: A test mode enable circuit 29 has a series of D type flip-flops 90 and 92. Each flip-flop is clock-operated by the specific logic level, which is applied to other terminal, and the detection of an overvoltage condition and plural flip-flops are provided against plural special test modes. Moreover, a power on reset circuit 40 is provided to lock out the entry to a test mode during the power up of the device. The acknowledgement of the entry to a test mode is given by supplying a low impedance to an output terminal, while the device is not enabled, and the chip enable of the device pulls put the device from the test mode. During a test mode, an output enable terminal OE of the device gives a chip enable function.