Title:
SEMICONDUCTOR MEMORY AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JP2004213722
Kind Code:
A
Abstract:
To provide a semiconductor memory operated even when a power supply voltage is lowered, realized by a simple structure, and easily formed by a logical process.
In a DRAM memory cell constituted of an access Tr103 and a cell capacitor 104, a depletion type MOSFET is used for the access Tr103 and the cell capacitor 104. As compared with a conventional case, an operation margin is larger, and the number of necessary power sources is lower.
Inventors:
YAMAZAKI HIROYUKI
HIROSE MASANOBU
HIROSE MASANOBU
Application Number:
JP2002379239A
Publication Date:
July 29, 2004
Filing Date:
December 27, 2002
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H01L21/8242; G11C11/404; G11C11/407; H01L27/108; H03K17/693; H03K19/00; H03K19/0175; H03K19/0948; H03K19/185; (IPC1-7): G11C11/404; G11C11/407; H01L21/8242; H01L27/108; H03K17/693; H03K19/00; H03K19/0175; H03K19/0948; H03K19/185
Attorney, Agent or Firm:
Hiroshi Maeda
Hiroshi Koyama
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Teshima Masaru
Atsushi Fujita
Hiroshi Koyama
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Teshima Masaru
Atsushi Fujita