To shorten the access time and to prevent a malfunction caused by a noise of an address signal by transmitting quickly an address signal to an internal circuit, with respect to a semiconductor memory.
Before activation of a control signal instructing a memory cell for operation, an address signal is transmitted to a decoder. At the time, the decoder is inactivated. After that, after the activation of a control signal, a new address signal is prohibited to receive, at the same time, the decoder is activated. Therefore, the decoder starts operation with a timing of quick operation cycle, and outputs a decoding signal. Consequently, an access time is shortened. Also, receiving a new address signal is prohibited after activation of a control signal. Therefore, decoding an erroneous address signal caused by a noise or the like by a decoder is prevented, and malfunction is prevented.
FUJIOKA SHINYA
FUJIEDA WAICHIRO
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