Title:
SEMICONDUCTOR MEMORY AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JP3817615
Kind Code:
B2
Abstract:
PURPOSE: To provide a semiconductor memory in which a large capacity can be realized without complicating manufacturing steps by forming a multilayer structure only to increase the capacity and a method for manufacturing the same.
CONSTITUTION: A first capacitor electrode 8 is interposed between a source and drain electrode 4 and a second capacitor electrode 10, thereby obtaining a large capacitor capacity with a small cell area. The electrode 4 and a gate electrode 7 are formed of the same polysilicon layer depositing step, and hence the same degree of the number of layers and the number of steps as those of a conventional stack type are provided, and there is no anxiety of complicating the structure and the steps. In addition, an impurity is introduced to a source and drain region 3 by diffusion from polysilicon to provide a shallow junction, thereby easily miniaturizing a transistor.
Inventors:
Yuichi Egawa
Application Number:
JP29233594A
Publication Date:
September 06, 2006
Filing Date:
October 31, 1994
Export Citation:
Assignee:
Lianhua Electronics Co., Ltd.
International Classes:
H01L27/04; H01L27/108; H01L21/822; H01L21/8242; (IPC1-7): H01L27/108; H01L21/8242; H01L27/04; H01L21/822
Domestic Patent References:
| JP5206399A | ||||
| JP2295160A |
Attorney, Agent or Firm:
Yoichi Oshima
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