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Title:
SEMICONDUCTOR MEMORY AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JPH05198768
Kind Code:
A
Abstract:

PURPOSE: To increase a capacitance of a capacitor by forming a lower electrode of a plurality of conductive layers, and forming an uneven surface on a side face of a laminate by utilizing a difference of etching rates.

CONSTITUTION: A first tungsten silicide layer is formed on a silicon substrate 40, a polycrystalline silicon layer is formed thereon, and further second tungsten silicide layers 9a, 9b, 9c are formed. A resist pattern 18 of a predetermined shape is formed on the surface of a second tungsten silicide layer. With the pattern as a mask the layers are etched. In this case, etching rates of the first, third layers and the second layer are different, and the three layers are so patterned along the shape of the resist 18 that the side face of the layer 9b is retracted from those of the first, second tungsten silicide layers. Thus, a recess is formed between the layers 9a and 9c. A dielectric element is formed along the uneven surface, and a capacitor having the uneven surface can be formed by covering the surface with an upper electrode.


Inventors:
NAKATANI YASUO
Application Number:
JP861792A
Publication Date:
August 06, 1993
Filing Date:
January 21, 1992
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L27/04; H01L21/02; H01L21/822; H01L21/8242; H01L27/10; H01L27/108; (IPC1-7): H01L27/04; H01L27/108
Domestic Patent References:
JPH0316258A1991-01-24
JPH0210762A1990-01-16
JPS63143840A1988-06-16
Attorney, Agent or Firm:
Fukami Hisaro (3 outside)