Title:
SEMICONDUCTOR MEMORY AND METHOD OF PRODUCTION
Document Type and Number:
Japanese Patent JP2838677
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To arrange a transferring transistor, a capacitor and a bit line on a same vertical line by forming semiconductor layers on the side surfaces of a gate electrode formed with a gate insulating films and on the side surfaces of a first and a second insulating films, and forming impurity regions on the side surfaces of the first and the second insulating films of the semiconductor layer.
SOLUTION: A first insulating film 51 is formed on a semiconductor substrate 30, and trenches 41 are formed on the first insulating film 51 and the semiconductor substrate 30. On the upper part of the trenches 41, a second insulating film 52 is formed thickly to fill all of the remaining parts of the trenches 41 on the upper parts of the trenches 41. A gate electrode is formed on the first insulating film 51 and on the side surface of the gate electrode, a gate insulating film 66 is formed. The semiconductor layers are formed on the side surfaces of the gate electrode formed with the gate insulating film 66 and on the side surfaces of the first and the second insulating films 51 and 52, impurity regions 69-1 and 69-2 are formed on the side surfaces of the first and the second insulating films 51 and 52 of the semiconductor layer. Therefore, a transferring transistor 60, a capacitor 40 and a bit line 70 are arranged on the vertical line.
Inventors:
ZON MUN CHOI
CHAN YORU KIMU
CHAN YORU KIMU
Application Number:
JP31583895A
Publication Date:
December 16, 1998
Filing Date:
November 10, 1995
Export Citation:
Assignee:
ERU JII SEMIKON CO LTD
International Classes:
H01L21/8242; H01L27/108; (IPC1-7): H01L27/108; H01L21/8242
Domestic Patent References:
| JP62169475A | ||||
| JP6425466A | ||||
| JP4212450A |
Attorney, Agent or Firm:
Masaki Yamakawa