Title:
半導体メモリ、半導体メモリの動作方法およびシステム
Document Type and Number:
Japanese Patent JP5136328
Kind Code:
B2
Abstract:
A memory includes a plurality of memory cells each of which includes a memory transistor and a selection transistor; a control gate line; a selection gate line; a source line; a bit line; a first driver that sets the control gate line and the selection gate line at a first voltage in a program operation; a second driver that sets the source line at a second voltage in the program operation, and sets the source line at a third voltage higher than the second voltage while the control gate line and the selection gate line are set at the first voltage; and a third driver that sets the bit line at a fourth voltage after the source line is set at the second voltage, the bit line being coupled to a memory cell being programmed.
Inventors:
Keisuke Watanabe
Application Number:
JP2008247604A
Publication Date:
February 06, 2013
Filing Date:
September 26, 2008
Export Citation:
Assignee:
Fujitsu Semiconductor Limited
International Classes:
G11C16/02; G11C16/04; G11C16/06
Domestic Patent References:
| JP2009211744A | ||||
| JP2005346819A | ||||
| JP11273388A | ||||
| JP10320988A | ||||
| JP2010518538A |
Attorney, Agent or Firm:
Furuya Fumio
Toshihide Mori
Toshihide Mori