PURPOSE: To increase memory capacity, by substantially forming a FET in planar type diffusion matching, and by making up a common source electrode by burying diffusion.
CONSTITUTION: An n+ epitaxial layer 2 and an n- epitaxial layer 3 are laminated on an n-type semiconductor substrate 1, and an oxide film 4 and a gate oxide film 5 are manufactured. A gate electrode 6 is selectively formed extending over the films 4, 5. When a p-layer 7 is diffused by the masks of the electrode 6 and the oxide film 4 and an n-layer 8 into the layer 7, the layers 7, 8 constitute diffusion self- matching. The whole surface is coated with an oxide film 9, an electrode window of the drain layer 8 is built up and Al wiring 10 is produced. Consequently, regions for wiring among source electrodes become useless and unit cell area can extremely be lessened by burying a source electrode common to all memory cells into the substrate, thus promoting the change of this memory storage into great capacity.
JPS5186978A | 1976-07-30 | |||
JPS49110250A | 1974-10-21 | |||
JPS51102476A | 1976-09-09 | |||
JPS49130692A | 1974-12-14 |