Title:
リフレッシュフラグを発生させる半導体メモリシステム
Document Type and Number:
Japanese Patent JP4961003
Kind Code:
B2
Abstract:
A semiconductor memory device includes an oscillator for generating an oscillator output signal; a refresh timer for generating a refresh pulse in response to predetermined first and second control signals, the oscillator output signal, and an external clock signal; a mode register set (MRS) unit for generating the first and second control signals in response to an address signal and an external command, the first control signal controlling time when the refresh pulse is generated by the refresh timer and the second control signal resetting the refresh timer; and a refresh controller for generating a refresh control signal in response to the refresh pulse, the refresh control signal refreshing a memory cell, wherein the refresh control signal is output as a refresh flag while the memory is refreshed.
Inventors:
Lee Jun-pei
Application Number:
JP2009230630A
Publication Date:
June 27, 2012
Filing Date:
October 02, 2009
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
G11C11/401; G11C11/406; G11C7/10
Domestic Patent References:
| JP6267273A | ||||
| JP2000353382A | ||||
| JP1302594A | ||||
| JP5342865A | ||||
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| JP8315569A | ||||
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| JP4026987A | ||||
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| JP57082287A |
Attorney, Agent or Firm:
Makoto Hagiwara