Title:
半導体メモリおよびシステム
Document Type and Number:
Japanese Patent JP5228472
Kind Code:
B2
Abstract:
A semiconductor memory is provided, the semiconductor memory including a memory core that includes a plurality of memory cells, a refresh generation unit that generates a refresh request for refreshing the memory cell, a core control unit that performs an access operation in response to an access request, a latency determination unit that activates a latency extension signal upon a conflict between activation of a chip enable signal and the refresh request and that deactivates the latency extension signal in response to deactivation of the chip enable signal, a latency output buffer that outputs the latency extension signal, and a data control unit that changes a latency from the access request to a transfer of data to a data terminal during the activation of the latency extension signal.
Inventors:
Shinya Fujioka
Application Number:
JP2007327678A
Publication Date:
July 03, 2013
Filing Date:
December 19, 2007
Export Citation:
Assignee:
Fujitsu Semiconductor Limited
International Classes:
G11C11/403; G06F12/00; G11C11/406; G11C11/407
Domestic Patent References:
| JP2007310959A | ||||
| JP200712244A |
Attorney, Agent or Firm:
Furuya Fumio
Toshihide Mori
Toshihide Mori