Title:
半導体メモリ試験装置
Document Type and Number:
Japanese Patent JP2527935
Kind Code:
B2
Abstract:
In a semiconductor test system, higher accuracy testing of semiconductor memories is achieved by providing test data from a modified pattern generator to identical addresses in both the memory under test and a buffer memory. This is achieved for various types of semiconductor memories by treating data generated by the modified pattern generator for the memory under tests in ways that would correspond to how the data is treated in various memories to be tested before storing the data in the buffer memory. This is accomplished using a variety of multiplexers and counters under control of a control signal generator. Data stored at locations with the same address in both memories is read out for comparison in a logic comparator. If the data is not identical, the semiconductor memory under test is rejected as defective.
Inventors:
大島 広美
清水 雅男
西浦 淳治
清水 雅男
西浦 淳治
Application Number:
JP11438186A
Publication Date:
August 28, 1996
Filing Date:
May 19, 1986
Export Citation:
Assignee:
株式会社 アドバンテスト
International Classes:
G01R31/28; G01R31/316; G01R31/3193; G11C29/00; G11C29/56; (IPC1-7): G01R31/28
Domestic Patent References:
| JPS57113500A | ||||
| JPH0668539A |
Attorney, Agent or Firm:
草野 卓