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Patent Searching and Data


Title:
SEMICONDUCTOR MEMORY UNIT
Document Type and Number:
Japanese Patent JPS5641583
Kind Code:
A
Abstract:

PURPOSE: To prevent reduction in readout rate by supplying an electric current providing hysteresis characteristics to a readout detecting circuit when a word line potential decreases below a fixed value.

CONSTITUTION: Emitters of transistors TX1... of memory cells DT1... are connected in common and a higher potential between word lines Vws and Vwn appears at the common connection line without fail. Then when all word lines decrease in potential down to a fixed value in address conversion, etc., the potential of the common connection line drops and hysteresis characteristic control circuit HC makes a comparison to reference voltage Vrs to supply hysteresis current Ish to a couple of transistors TL1 and TL2 of the prior stage of the sense amplifier. Therefore, control by the hysteresis current to prevent a readout value, the intermediate value between "1" and "0", from getting unstable in address switching, etc., is exercised only as the occasion demands, so that an excellent read of even an L capacity memory cell with a noise, etc., prevented will be taken without lowering the readout rate.


Inventors:
TAKAHASHI YUKIO
Application Number:
JP10739479A
Publication Date:
April 18, 1981
Filing Date:
August 23, 1979
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G11C11/41; G11C7/06; G11C11/416; (IPC1-7): G11C11/34