Title:
SEMICONDUCTOR MEMORY AND WORD LINE DRIVE METHOD
Document Type and Number:
Japanese Patent JP3450239
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To solve such problems that hitherto, when a selection word line is continued, that is, as capability cannot help being decided supposing a case in which a load is maximum, a boosting circuit is operated exceeding actual word line current consumption and a current is consumed excessively, and also it is hard to apply the device to a memory LSI operated at high speed.
SOLUTION: Word line transition is detected by an address latch 11, an EX-OR circuit 12, and an OR circuit 13 instead of boosting circuit voltage, and an output counter value of a counter 14 is varied. A boosting circuit 15 has such capability that the circuit receives the counter output value of the counter 14 and varies current capability supplied to a word driver 17, corresponding to the counter output value. As optimum current capability just enough is set to the boosting circuit 15 according to the magnitude of the load, power consumption can be suppressed. Also, the device is easily applied to the memory LSI which operates at a high speed.
More Like This:
| JPH0684355 | LOW-VOLTAGE DRIVING SEMICONDUCTOR MEMORY |
| JP3710703 | SEMICONDUCTOR INTEGRATED CIRCUIT |
| JP2501993 | SEMICONDUCTOR MEMORY |
Inventors:
Shigeru Kuhara
Application Number:
JP33238199A
Publication Date:
September 22, 2003
Filing Date:
November 24, 1999
Export Citation:
Assignee:
NEC Electronics Corporation
International Classes:
G11C11/413; G11C11/407; (IPC1-7): G11C11/407; G11C11/413
Domestic Patent References:
| JP7282590A | ||||
| JP5101655A | ||||
| JP8315570A |
Attorney, Agent or Firm:
Kaneyuki Matsuura