To reduce power consumption of row selecting operation and to secure operation margin by suppressing a noise at the time of read-out of data in a semiconductor memory provided with a memory array in which two transistor cells are arranged with half pitch.

A memory array 20 has a plurality of cell units CU corresponding to intersections of word lines and bit lines arranged along respectively the row direction and the column direction. Every adjacent two pieces out of cell units selected by the same word line constitute the same memory cell MC. Two bit lines corresponding to every two cell units constituting each memory cell belonging to the same memory cell column constitute pairs of bit lines. One of two bit lines constituting other pair of bit lines is arranged between two bit lines constituting the same pair of bit line.