To provide a semiconductor memory in which the number of wirings in a central part can be reduced.
A semiconductor memory 100 is provided with banks 10-13, pre-decoders 14, 15, a latch circuit 16, a counter 17, a fuse 18, buffers 19, 20. The banks 10-13 comprise a plurality of memory cells arranged in a matrix state or the line. The pre-decoders 14, 15 are arranged at a central part of the semiconductor memory 100. The pre-decoder 14 generates a pre-decode signal for selecting each of banks 12, 13 based on bank addresses BA0, BA1 inputted from the buffer 20 and outputs a pre-decode signal to the banks 12, 13, the pre-decoder 15 generates a pre-decode signal for selecting each of banks 10, 11 based on bank addresses BA0, BA1 and outputs a pre-decode signal to the banks 10, 11.
| JP2001167570 | LINE MEMORY DEVICE |
| JPH0684381 | SEMICONDUCTOR INTEGRATED CIRCUIT |
YONETANI HIDEKI
ISHIDA KOZO
JINBO SHINICHI
SUWA MASATO
YAMAUCHI TADAAKI
MATSUMOTO JUNKO
DEN MASUNARI
OKAMOTO TAKEO
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